This invention relates in general to television tuning systems and in particular to a microcomputer-controlled automatic frequency synthesis television tuning system for rapidly tuning to a selected channel.
With the ever-increasing number of available television channels, increased operating demands are being placed upon television receiver tuning systems. One operating parameter of increasing importance is the ability of the receiver's tuner to rapidly tune from one channel to another selected channel. Today larger inter-channel frequency ranges must be traversed more frequently than heretofore. Decreased channel acquisition time, i.e., the maximum time it takes to tune from any one channel to another, has obvious advantages from the viewer's standpoint.
Frequency synthesizing tuning systems offer many advantages including enhanced tuning accuracy and, as a result, are being employed on an ever increasing basis in current production tuning systems. One frequency synthesizer currently in common use is termed the indirect frequency synthesizing tuning system in that it uses a programmable phase-locked loop for controlling and maintaining a desired output frequency. This tuning approach offers the advantages of relatively low cost, improved frequency stability, and wide bandwidth coverage. The primary limitation of frequency synthesizers incorporating a phase-locked loop relates to their relatively slow inter-channel tuning rate. This operating limitation of frequency synthesizing tuners having a phase-locked loop severely limits their utility in applications involving a very rapid change from one output frequency to another desired output frequency. Thus, there is a substantial need for a tuning system possessing the advantages of a frequency synthesizer with a phase-locked loop while also providing rapid tuning from one channel to another, far-removed channel upon the receipt of the appropriate command from a user.
One example of a rapid tuning circuit for high frequency receivers is disclosed in U.S. Pat. No. 4,114,100 to Klank wherein is described a tuning circuit which compares a first number identifying the frequency of the received channel with a second number provided by an input keyboard which represents the desired channel to which the receiver is to be tuned. Two numbers each representing one of the aforementioned channels are compared digit by digit starting with the most significant digit of each in a comparator which provides three different outputs. One output represents identical frequency inputs provided to it, a second output provides a signal when the digit representation at its one input represents a value larger than that of the digit representation at its other input, and a third output provides a signal when the digit representation at its one input represents a value smaller than that of the digit representation and its other input. The number of reversals of the inequality represented by the output of this comparator determines the respective level of the rate of change of the tuning voltage. The smaller the number of changes in inequality results, i.e., the smaller the difference between the two numbers, the lower the tuning rate. Although capable of rapid tuning, this invention only indirectly tunes to the desired frequency in an oscillatory manner and as a result suffers from inherent inaccuracy over relatively short tuning periods.
Another approach to high speed tuner design is disclosed in U.S. Pat. No. 4,105,948 to Wolkstein wherein is described a two-step frequency synthesizing tuner in which a high speed digital signal provides an initial rapid change in the output frequency of a local oscillator to a value near the desired value followed by a second control voltage coupled to a phase-lock loop to pull the oscillator frequency to the desired output frequency. While this approach is capable of initial rapid tuning, this high speed tuning rate is achieved only at the initial instant of frequency change which is measured in nanoseconds and therefore fails to maintain a high speed tuning change rate for any substantial duration. Still other approaches to a high speed tuning system are disclosed in U.S. Pat. Nos. 4,070,629 and 4,156,197 both to Merrell. In the tuning system described in both of these patents channel acquisition time is reduced by initially overriding the phase comparator in a phase-lock loop and ramping the tuning system toward the desired frequency until that frequency is passed at which time normal phase-lock loop tuning occurs. Thus, when a channel number input is made, the system goes into full ramping, senses when the desired frequency has been passed, operates for a fixed time in a single frequency mode (with a PLL) and releases to a tuning window mode with AFC. The invention is directed to a 100% ramping feature, i.e., driving the varactor-controlled oscillator to rapidly change frequency, until an overshoot condition is detected, which shortens the channel acquisition, or tuning, time. This approach places high demands on overshoot voltage detection which must not only be accurately detected, but also sensed immediately after tuning voltage crossing.
These and other limitations encountered in the prior art are avoided by the present invention which initially ramps quickly toward the selected channel and then automatically and incrementally reduces tuning speed as the proper frequency is approached. This multiple step tuning rate change approach permits direct and accurate tuning to the selected channel.